1. Field of the Invention
The present invention relates to a liquid crystal display device, and more particularly, to an array substrate for a liquid crystal display device.
2. Description of Related Art
Generally, liquid crystal display (LCD) devices make use of optical anisotropy and polarization properties of liquid crystal molecules to control alignment orientation. The alignment direction of the liquid crystal molecules can be controlled by application of an electric field. Accordingly, when the electric field is applied to liquid crystal molecules, the alignment of the liquid crystal molecules changes. Since refraction of incident light is determined by the alignment of the liquid crystal molecules, display of image data can be controlled by changing the applied electric field.
Of the different types of known LCDs, active matrix LCDs (AM-LCDs), which have thin film transistors and pixel electrodes arranged in a matrix form, are of particular interest because of their high resolution and superiority in displaying moving images. Because of their light weight, thin profile, and low power consumption characteristics, LCD devices have wide application in office automation (OA) equipment and video units. A typical liquid crystal display (LCD) panel may include an upper substrate, a lower substrate and a liquid crystal layer interposed therebetween. The upper substrate, commonly referred to as a color filter substrate, may include a common electrode and color filters. The lower substrate, commonly referred to as an array substrate, may include switching elements, such as thin film transistors (TFTs), and pixel electrodes.
LCD device operation is based on the principle that the alignment direction of the liquid crystal molecules is dependent upon an electric field applied between the common electrode and the pixel electrode. Moreover, because the liquid crystal molecules have spontaneous polarization characteristics, the liquid crystal layer is considered an optical anisotropy material. As a result of the spontaneous polarization characteristics, the liquid crystal molecules possess dipole moments when a voltage is applied to the liquid crystal layer between the common electrode and pixel electrode. Thus, the alignment direction of the liquid crystal molecules is controlled by the application of an electric field to the liquid crystal layer. When the alignment direction of the liquid crystal molecules is properly adjusted, incident light is refracted along the alignment direction to display image data. The liquid crystal molecules function as an optical modulation element having variable optical characteristics that depend upon polarity of the applied voltage.
FIG. 1 shows a conventional LCD device. The LCD device 11 includes an upper substrate 5 and a lower substrate 22 with a liquid crystal layer 14 interposed therebetween. The upper substrate 5 and the lower substrate 22 are commonly referred to as a color filter substrate and an array substrate, respectively. Within the upper substrate 5 and upon the surface opposing the lower substrate 22, a black matrix 6 and a color filter layer 7 are formed in the shape of an array matrix and include a plurality of red (R), green (G), and blue (B) color filters so that each color filter is surrounded by corresponding portions of the black matrix 6. Additionally, a common electrode 18 is formed on the upper substrate 5 to cover the color filter layer 7 and the black matrix 6. In the lower substrate 22 and upon the surface opposing the upper substrate 5, a thin film transistor (TFT) “T,” is formed in the shape of an array matrix corresponding to the color filter layer 7. A plurality of crossing gate lines 13 and data lines 15 are positioned such that each TFT “T” is located adjacent to each crossover point of the gate lines 13 and the data lines 15. Furthermore, a plurality of pixel electrodes 17 are formed on a pixel region “P” defined by the gate lines 13 and the data lines 15 of the lower substrate 22. The pixel electrode 17 includes a transparent conductive material having good transmissivity such as indium-tin-oxide (ITO) or indium-zinc-oxide (IZO), for example.
According to the LCD device 11 of FIG. 1, a scanning signal is applied to a gate electrode of the TFT “T” through the gate line 13, while a data signal is applied to a source electrode of the TFT “T” through the data line 15. As a result, the liquid crystal molecules of the liquid crystal layer 14 are aligned and arranged by operation of the TFT “T,” and incident light passing through the liquid crystal layer 14 is controlled to display an image.
FIG. 2A is a plan view showing a pixel of a conventional array substrate for use in a liquid crystal display device. In FIG. 2, an array substrate 22 includes a pixel region “P” having a corresponding thin film transistor (TFT) “T,” a pixel electrode 17 and a storage capacitor “C.” Gate lines 13 are arranged in a transverse direction and data lines 15 are arranged in a longitudinal direction such that each pair of the gate lines 13 and the data lines 15 define a pixel region “P.” The TFT “T” includes a gate electrode 26, a source electrode 28, a drain electrode 30 and an active layer 33. The gate electrode 26 of the TFT “T” extends from the gate line 13, while the source electrode 28 of the TFT “T” extends from the data line 15. The drain electrode 30 is spaced apart from the source electrode 28 and the active layer 55 is disposed over the gate electrode 24 between the source electrode 28 and the drain electrode 30. The source electrode 28 and the drain electrode 30 overlap opposite ends of the gate electrode 26. A portion of the pixel electrode 17 overlaps a portion of the drain electrode 30 and electrically contacts the drain electrode 30 through a drain contact hole 41. Furthermore, the storage capacitor “C” is a storage-on-gate type capacitor, and thus comprises a capacitor electrode 16 electrically communicating with a pixel electrode 17 through a capacitor contact hole 43, a portion of the gate line 13, and an insulator functioning as a dielectric layer (not show in FIG. 2). Namely, the storage capacitor “C” has M/I/M (metal/insulator/metal) structure. At this point, the position and configuration of the storage capacitor “C” can be various.
In the above-described structure, a parasitic capacitor is formed between the gate electrode 26 and the drain electrode 28 of the TFT “T.” The parasitic capacitance influences and deteriorates function of the liquid crystal layer since the parasitic capacitance is a direct-current component of the voltage. Furthermore, the gate electrode 26 and the drain electrode 28 of the TFT “T” can become short-circuited if the gate insulation layer disposed on the gate electrode 26 has defects, such as pinholes or cracks. Accordingly, the gate insulation layer in a conventional array substrate, which is used as a dielectric layer in the storage capacitor “C,” is formed of a relatively large thickness over the gate electrodes and gate lines.
Thin film transistors (TFTs) can be divided into two generally different categories based upon the relative disposition of their gate electrodes—staggered types and coplanar types. The staggered type TFT includes an inverted staggered type which is generally used for LCD devices due to their simple structure and superior efficiency. Within the inverted staggered type TFT there includes a back channel etched type (EB) and an etch stopper type (ES). A manufacturing method of the back channel etched type TFT will be explained hereinafter.
FIGS. 3A to 3J are plan views and cross-sectional views each taken along the line III-III of corresponding plan view and illustrates conventional manufacturing processes of an array substrate of FIG. 2B.
Referring to FIG. 3A, a substrate 22 is cleaned of organic materials and any foreign substances to promote adhesion with a first metal layer that is subsequently deposited on the substrate 22 by a sputtering process, for example. Here, the first metal layer is aluminum or aluminum alloy, such as aluminum neodymium (AlNd), for example. Then, the first metal layer is subsequently patterned using a first mask to form the gate lines 13 in a transverse direction and a gate electrode 26 that extends from the gate line 13. In the conventional array substrate, aluminum is conventionally used as a metal for the first metal layer because of its low resistance and reduced RC delay. However, pure aluminum is chemically weak when exposed to acidic fabrication processing, thereby resulting in formation of hillocks during high temperature fabrication processing. Accordingly, aluminum alloys and double-layered structure are used for the first metal layer. When employing the double-layered structure for the gate electrode 26 and gate line 13, the aluminum (Al) layer or the aluminum alloy layer is stacked with a molybdenum (Mo) layer or a chrome (Cr) layer that has high corrosion resistance and durability.
In FIG. 3A, the gate insulation layer 33 is formed on a surface of the substrate 22 to cover the patterned first metal layer. Then, a pure amorphous silicon (a-Si:H) layer 53 and a doped amorphous silicon (n+ a-Si:H) layer 54 are sequentually formed upon the gate insulation layer 33. The gate insulation layer is an inorganic material, such as silicon nitride (SiNx) or silicon oxide (SiOx), or an organic material, such as benzocyclobutene (BCB) or acryl-based resin, for example.
FIG. 3B shows a second mask fabrication process in which the pure amorphous silicon layer and doped amorphous silicon layer are patterned. A photo resist is formed on the doped amorphous silicon layer and then exposed to light using the second mask. Thereafter, the photo resist is developed to form a patterned photo resist 35 over the gate electrode 26 and to expose the doped amorphous silicon layer.
In FIGS. 3C and 3D, an exposed portion of the doped amorphous silicon layer 54 is removed, and a portion of the pure amorphous silicon layer 53 is also removed to form an active layer 55 and an ohmic contact layer 56. Accordingly, a semiconductor layer 58 including the active layer 55 and ohmic contact layer 56 are formed on the gate insulation layer 33 disposed over the gate electrode 26. As a result of this fabrication process, the gate insulation layer 33 is exposed except for a portion disposed over the gate electrode 26.
In FIGS. 3E and 3F, a second metal layer is formed upon the ohmic contact layer 56 and upon the gate insulation layer 33 by depositing a metallic material, such as molybdenum (Mo), chrome (Cr), tungsten (W), aluminum (Al), aluminum alloy or an alloy thereof. The second metal layer is subsequently patterned using a third mask to form a source electrode 28, a drain electrode 30, a data line 15, and a capacitor electrode 16. The data line 15 is arranged perpendicular to the gate line 13 and defines a pixel region “P” with a data line 13. The source electrode 28 extends from the data line 15 and overlaps an end portion of the gate electrode 26. The drain electrode 30 is space apart from the source electrode 28 and overlaps an opposite end portion of the gate electrode 26. Thus, a thin film transistor (TFT) “T” is formed. Moreover, the capacitor electrode 16 is disposed over a portion 13a of the gate line 13. Therefore, a storage capacitor “C” comprises the portion 13a of the gate line 13 as a first capacitor electrode, a portion of gate insulation layer 33 as a dielectric layer, and the capacitor electrode 16 as a second capacitor electrode. Since the capacitor electrode 16 is formed over the portion 13a of the gate line 13, the structure is commonly referred to as a storage-on-gate structure. If the second metal layer is formed of aluminum in the above-described structure, molybdenum (Mo) or chrome (Cr) is disposed on the second metal layer in order to form a double-layered structure.
In FIGS. 3E and 3F, a portion of the ohmic contact layer 56 disposed upon the active layer 55 is etched using the source electrode 28 and drain electrode 30 as masks, thereby forming a channel region in the active layer 55 between the source electrode 28 and the drain electrode 30.
In FIGS. 3G and 3H, a passivation layer 39 is formed on the TFT “T,” on the storage capacitor “C” and on the gate insulation layer 33. The passivation layer 39 is subsequently patterned using a fourth mask to form a drain contact hole 41 to the drain electrode 30 and a capacitor contact hole 43 to the capacitor electrode 16.
In FIGS. 3I and 3J, a transparent conductive material is deposited on the patterned passivation layer 39. The transparent conductive material commonly includes indium tin oxide (ITO) or indium zinc oxide (IZO). Thereafter, the transparent conductive material is patterned to form a pixel electrode 17 in the pixel region “?.” A portion of the pixel electrode 17 overlaps the drain electrode 30 and electrically contacts the drain electrode 30 through the drain contact hole 41. Additionally, another portion of the pixel electrode 17 overlaps the portion 13a of the gate line 13 and the capacitor electrode 16, thereby electrically contacting the capacitor electrode 16 through the capacitor contact hole 43.
As described above, the gate insulation layer is commonly formed of a relatively large thickness to prevent any short-circuit between the gate electrode and the drain electrode in the thin film transistor. Thus, the dielectric layer that is the portion of the gate insulation layer also is formed of a relatively large thickness in the storage capacitor. As commonly known, the capacitance of the storage capacitor is inversely proportion to the thickness of the dielectric layer. Accordingly, the storage capacitor fabricated by the above-described fabrication method does not have sufficient capacitance, thereby causing an image-sticking defect when displaying a subsequent image after displaying a previous image.